1. Field of the Invention
This invention relates to an electronic computer-aided system, and particularly to a method of optimizing a scan chain ordering in circuit designs involving latches therein.
2. Description of Background
When designers design custom macros or circuit designs involving latches or flip-flops they must also implement a scan chain. A scan chain is a technique used to test various circuit designs involving latches, where each latch is wired together to form the scan chain in which each latch is tested and observed by the designer using design automation software where the designer can graphically build the circuit design through a schematic and layout representation.
When designing integrated circuits involving latches, levels and sublevels of hierarchy are formed, where each level and sublevel include a number of latches grouped in one or more cells in the hierarchy. Each cell is designed to include a cell scan input pin and a cell scan output pin, where every cell scan input pin of one cell is wired to a cell scan output pin of another cell, thereby forming a scan chain. Of the cells in the scan chain, one cell scan input pin of a cell in the scan chain is wired to a primary circuit scan input pin and one cell scan output pin of another cell in the scan chain is wired to a primary circuit scan output pin. Within each cell, the latch scan input pin of each latch is wired to a latch scan output pin of another latch within the cell. The primary circuit scan input pin is where the scan chain begins and the primary circuit scan output pin is where the scan chain ends. In general terms, during scan testing, designers send a predetermined pattern through the cells in the order of the scan chain at the primary circuit scan output pin and out the primary circuit scan output pin where the designer can obtain the status of the latches in the scan chain. As such, the designer can determine the state of each latch within the integrated circuit.
During the schematic build process, the designer usually follows the convention of a hardware description language, such as Verilog or VHDL to hook up the scan chain. This is usually done for correspondence purposes for logic checking. However, the scan chain is usually not an optimal hook-up because it is not placement driven. Once the placement is made in the layout process, the designer must go back to the schematic and make the scan chain location driven to minimize wires and resources. However, this usually involves messy pin additions, wire namings, and a messy style. Updating the schematic to reflect the location driven scan chain may also be timely.